As the dimensions of transistors are scaled down, the reduction of vertical junction depth and the suppression of dopant lateral diffusion, in order to control short-channel effects, become greater challenges. MOS devices have become so small that the diffusion of impurities from source/drain extension regions and deep source/drain regions will significantly affect the characteristics of the MOS devices. Particularly, impurities from source/drain extension regions are readily diffused into the channel region, causing short channel effects and leakage currents between the source and drain regions. Methods for controlling diffusion are thus explored.
A first method of confining the diffusion of p-type or n-type impurities is discussed below. As is shown in FIG. 1, a gate electrode 6 is formed over a substrate 2. N-type dopants and/or p-type dopants are introduced into the gate electrode 6 and source/drain regions 8 of NMOS devices and PMOS devices, respectively. Arrows 10 symbolizes the implantation. For n-type devices, nitrogen and fluorine are co-implanted to source/drain regions 8, and for p-type devices, nitrogen and carbon are co-implanted to source/drain regions 8. Nitrogen, carbon, and fluorine have the function of retarding the diffusion of dopants. Therefore, the diffusion of the dopants is controlled when the MOS devices are annealed, and thus the source/drain regions 8 have higher impurity concentrations and more confined profiles.
A second method for confining the profile of phosphorus in deep source/drain regions 16 of NMOS devices is illustrated in FIG. 2. After the formation of a gate electrode 12 over a substrate 20, LDD regions 14 are formed by introducing an n-type dopant such as arsenic. Spacers 11 are then formed. Symbolized by arrows 22, phosphorus is introduced to form deep source/drain regions 16. Carbon or fluorine is also implanted into the same regions. The addition of carbon or fluorine makes relatively high concentrations of phosphorus possible since less is diffused away, and transistor drive current is improved without unduly compromising the short channel characteristics.
For high performance devices, shallow and highly activated lightly doped source/drain (LDD) regions are desired. Typically, arsenic is preferred for forming LDD regions for its low diffusion length. However, the corresponding sheet resistance is relatively high due to its low activation level, thus limiting device performance, such as drive currents, of NMOS devices. Another commonly used n-type dopant, phosphorus, is known to have a high activation level but a long diffusion length, thus the junction depth is adversely affected, and diffusion into the channel region is also significant. Therefore, the formation of shallow and highly activated LDD regions is one of the challenges in integrated circuit fabrication technologies.